The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and designs have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometry size (e.g., the smallest component that can be created using a fabrication process) has decreased. As geometry size gets smaller, the packaging process of ICs becomes more challenging.
One of the current packaging processes employs “flip chip” technology, where a chip is flipped and bonded with a carrier substrate in a post-SMT (surface mount) process. Temperature fluctuations in existing flip chip bonding processes may result in excessive thermal stress, which may then lead to warping of the chip package. FIG. 1 shows a semiconductor device having a die 120 mounted onto a substrate 110 and the semiconductor device undergoing warpage due to CTE (coefficient of thermal expansion) mismatch between the die 120 and the substrate 110. As the die 120 and the substrate 110 undergo temperature changes during the flip chip bonding process, the die 120 and the substrate 110 will contract at rates that are dependent on their respective coefficients of thermal expansion. Often times, there is a mismatch between the CTE of the die 120 and the CTE of the substrate 110. This mismatch of the CTE means that the die 120 and the substrate 110 are contracting at different rates, which causes stress between the die 120 and the substrate 110.
In one example, due to the large mismatch in CTE between a chip and a flexible substrate, which can be mostly composed of polyimide and copper layers, the warpage of the die can be as large as 100 nm. Such large warpage can exceed the surface flatness requirements (e.g., 20-30 nm) required by many sensor application systems such as optical and capacitance-type fingerprint recognition systems.
Although the post-SMT die warpage can be effectively reduced by simply increasing the die thickness, the total package stack-up height constraint, which is virtually adopted by all applications using flexible substrate, makes this not a viable option.